Nested loops on contemporary processor architectures

Speaker: 

Beata Bylina i Jarosław Bylina, Uniwersytet Marii Curie-Skłodowskiej w Lublinie

Date: 

30/11/2016 - 12:00

Nested loops occur very often in numerical problems. The aim of the presentation is to show various strategies of parallelizing nested loops on modern architectures -- like Intel Xeon and Intel Xeon Phi. We employ both parallelism and vectorization to accelerate nested loops. It is possible to shorten the runtime when utlilizing the appropriate strategies with the use of good scheduling.

We do it on the example of the WZ factorization. In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step what makes the problem more interesting.

Seminar photos: 
Beata Bylina, Jarosław Bylina - Zagnieżdżone pętle na współczesnych architekturach procesorówBeata Bylina, Jarosław Bylina - Zagnieżdżone pętle na współczesnych architekturach procesorówBeata Bylina, Jarosław Bylina - Zagnieżdżone pętle na współczesnych architekturach procesorówBeata Bylina, Jarosław Bylina - Zagnieżdżone pętle na współczesnych architekturach procesorów

Historia zmian

Data aktualizacji: 18/06/2018 - 09:27; autor zmian: ()

Nested loops occur very often in numerical problems. The aim of the presentation is to show various strategies of parallelizing nested loops on modern architectures -- like Intel Xeon and Intel Xeon Phi. We employ both parallelism and vectorization to accelerate nested loops. It is possible to shorten the runtime when utlilizing the appropriate strategies with the use of good scheduling.

We do it on the example of the WZ factorization. In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step what makes the problem more interesting.

Data aktualizacji: 30/11/2016 - 13:52; autor zmian: ()

Nested loops occur very often in numerical problems. The aim of the presentation is to show various strategies of parallelizing nested loops on modern architectures -- like Intel Xeon and Intel Xeon Phi. We employ both parallelism and vectorization to accelerate nested loops. It is possible to shorten the runtime when utlilizing the appropriate strategies with the use of good scheduling.

We do it on the example of the WZ factorization. In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step what makes the problem more interesting.

Data aktualizacji: 30/11/2016 - 13:29; autor zmian: ()

Nested loops occur very often in numerical problems. The aim of the presentation is to show various strategies of parallelizing nested loops on modern architectures -- like Intel Xeon and Intel Xeon Phi. We employ both parallelism and vectorization to accelerate nested loops. It is possible to shorten the runtime when utlilizing the appropriate strategies with the use of good scheduling.

We do it on the example of the WZ factorization. In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step what makes the problem more interesting.

Data aktualizacji: 28/11/2016 - 16:18; autor zmian: Piotr Gawron (gawron@iitis.pl)

Nested loops occur very often in numerical problems. The aim of the presentation is to show various strategies of parallelizing nested loops on modern architectures -- like Intel Xeon and Intel Xeon Phi. We employ both parallelism and vectorization to accelerate nested loops. It is possible to shorten the runtime when utlilizing the appropriate strategies with the use of good scheduling.

We do it on the example of the WZ factorization. In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step what makes the problem more interesting.

Data aktualizacji: 28/11/2016 - 16:17; autor zmian: Piotr Gawron (gawron@iitis.pl)